Systems Engineering FAQ

Answers by Robert Halligan FIE Aust CPEng IntPE(Aus).

VHDL is a hardware description language used in the design of FPGAs. Why do you describe it as a requirements language?


Although VHDL has “Hardware Description Language” in its name, its behavioral modeling syntax includes logic operators, viz.: and, or, nand, nor, xor, xnor and not, plus other types of operators such as relational, shift, and arithmetic, enabling solution-free behaviour to be specified. VHDL does not require components to be defined; it is capable of black-box behavioural description. Ipso facto, VHDL is a requirements language (but not only a requirements language, it is also a design language). The same is true for many other behavioral modeling languages – they can be used to describe both requirements and design.


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Published 2 years ago


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